Estimation of WCET using a little language to describe microcontrollers and DSPs architectures

A method for analysing and predicting the timing properties of a program fragment will be described. First a little language implemented to describe a processor’s architecture is presented followed by the presentation of a new static WCET estimation method. The timing analysis starts by compiling a processor’s architecture program followed by the disassembling of the program fragment. After sectioning the assembler program into basic blocks call graphs are generated and these data are later used to evaluate the pipeline hazards and cache miss that penalize the real-time performance. Some experimental results of using the developed tool to predict the WCET of code segments using some Intel microcontroller are presented. Finally, some conclusions and future work are presented

An automatic programming tool for heterogeneous

Recent advances in network technology and the higher levels of circuit integration due to VLSI have led to widespread interest in the use of multiprocessor systems in solving many practical problems. As the hardware continues to diminish in size and cost, new possibilities are being created for systems that are heterogeneous by design. Parallel multiprocessor architectures are now feasible and provide a valid solution to the throughput rates demands of the increasing sophistication of control and/or instrumentation systems. Increasing the number of processors and the complexity of the problems to be solved makes programming multiprocessor systems more difficult and error-prone. This paper describes some parts already implemented (mainly the scheduler) of a software development tool for heterogeneous multiprocessor system that will perform automatically: code generation, execution time estimation, scheduling and handles the communication primitive insertion

A machine independente wCET predictor for microcontrollers and DSPs

This paper describes a method for analyzing and predicting the timing properties of a program fragment. The paper first presents a little language implemented to describe a processor’s architecture and a static WCET estimation method is then presented. The timing analysis starts by compiling a processor’s architecture program followed by the disassembling of the program fragment. The assembler program is then decomposed into basic blocks and a call graph is generated. These data are later used to evaluate the pipeline hazards and cache miss that penalize the real-time performance. Finally, some experimental results of using the developed tool to predict the WCET of code segments with some Intel microcontroller are presented. execution, the desired time will be found by averaging. Even with this approach, if you want an accurate measurement, a number of complications such as, compiler optimizations, operating system distortions, must be solved. Nevertheless, these approaches are unrealistic since they ignore the system interferences and the effects of cache and pipeline, two very important features of some processors that can be used in our hardware architecture. Shaw [1], Puschner [2], and Mok [3], developed some very elaborated methodology for WCET estimation, but none of them takes into account the effects of cache an

A scheduling framework for heterogenous multiprocessor architectures based on industrial processors (DSP and microcontrollers)

Current VLSI and networking technology, the increase in computational power, and the rapid decrease in computational cost, enable the interconnection of VLSI processors, which can be arranged on a functional decomposition of the computational task to exploit the potential of multiprocessing. The use of multiprocessor systems in such way, provides a novel and cost effective solution in solving many practical problems in signal processing, control systems, instrumentation systems and robotics. In this article we present a framework that addresses the specificities of industrial processors, such as DSPs and microcontrollers and can easily be used to implement a huge range of scheduling algorithms

Design of an energy supply and demand forecasting system based on web crawler and a grey dynamic model

An energy supply and demand forecasting system can help decision-makers grasp more comprehensive information, make accurate decisions and even plan a carbon-neutral future when adjusting energy structure, developing alternative energy resources and so on. This paper presents a hierarchical design of an energy supply and demand forecasting system based on web crawler and a grey dynamic model called GM(1,1) which covers all the process of data collection, data analysis and data prediction. It mainly consists of three services, namely Crawler Service (CS), Algorithm Service (AS), Data Service (DS). The architecture of multiple loose coupling services makes the system flexible in more data, and more advanced prediction algorithms for future energy forecasting works. In order to make higher prediction accuracy based on GM(1,1), this paper illustrates some basic enhanced methods and their combinations with adaptable variable weights. An implementation for testing the system was applied, where the model was set up for coal, oil and natural gas separately, and the enhanced GM was better with relative error about 9.18% than original GM on validation data between 2010 and 2020. All results are available for reference on adjusting of energy structure and developing alternative energy resources.This research was funded by NSFC grant number 61972174, Guangdong Science and Technology Planning Project grant number 2020A0505100018, Guangdong Universities’ Innovation Team Project grant number 2021KCXTD015, Guangdong Key Disciplines Project grant number 2021ZDJS138, and 2021 University-level Teaching Quality Project grant number ZLGC20210203

Calibration of a multi-load cells weighing system based on neural networks

Multi-load cells weighting systems are based on a platform supported by four or more load cells, normally in parallel inputting lhe same signal conditioning unit. Because of mechanical and electrical paralleling tuning the gain of a load cell affects lhe behavior of the others, making the calibration difficult and tedious, specially withweightbridges for cars and trucb, requiring lhemotion of heavy weights around /arge p/atforms

The portal protein plays essential roles at different steps of the SPP1 DNA packaging process

AbstractA large number of viruses use a specialized portal for entry of DNA to the viral capsid and for its polarized exit at the beginning of infection. These families of viruses assemble an icosahedral procapsid containing a portal protein oligomer in one of its 12 vertices. The viral ATPase (terminase) interacts with the portal vertex to form a powerful molecular motor that translocates DNA to the procapsid interior against a steep concentration gradient. The portal protein is an essential component of this DNA packaging machine. Characterization of single amino acid substitutions in the portal protein gp6 of bacteriophage SPP1 that block DNA packaging identified sequential steps in the packaging mechanism that require its action. Gp6 is essential at early steps of DNA packaging and for DNA translocation to the capsid interior, it affects the efficiency of DNA packaging, it is a central component of the headful sensor that determines the size of the packaged DNA molecule, and is essential for closure of the portal pore by the head completion proteins to prevent exit of the DNA encapsidated. Functional regions of gp6 necessary at each step are identified within its primary structure. The similarity between the architecture of portal oligomers and between the DNA packaging strategies of viruses using portals strongly suggests that the portal protein plays the same roles in a large number of viruses

Teaching with internet support : a case example

The evolution of Internet and all related technologies contributed, a lot, for the development of the e-learning. This paper discusses the advantages in using the new Technologies, namely the Internet, as an aid tool to teaching, and presents an example developed in the Degree of Industrial Electronics and Computer Engineering at University of Minho. It also discusses the motivations of the students on acquiring knowledge by an alternative method of teaching/learning.The authors are grateful to FCT (Fundação para a Ciência e a Tecnologia), projects funding POCTI/ESE/41170/2001 and POCTI/ESE/48242/2002

Estudo das técnicas de medição do auto amortecimento de cabos condutores

Trabalho de conclusão de curso (graduação)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Mecânica, 2014.Este trabalho visa o estudo das técnicas de medição de auto amortecimento de cabos condutores. Nesse sentido, é abordada a fundamentação teórica necessária a implementação desse tipo de ensaio. Com base na revisão bibliográfica foram identificados três enfoques para a realização dos procedimentos experimentais (Decaimento Logarítmico, Método da Potência e Método da Onda Estacionária). Após o estudo desses métodos, foram selecionados a implementação experimental dos Métodos da Potência e da Onda Estacionaria e descritas as rotinas que serão utilizadas na bancada de ensaios do LABCABOS/UnB. ______________________________________________________________________________ ABSTRACTThis work aims at the study of measuring techniques of self-damping of cables. In this sense, is addressed the theoretical foundation required the implementation of this type of test. On the basis of the literature review were identified three approaches to the implementation of the experimental procedures (Logarithmic Decay, Method of Power and Method of Standing Wave). After the study of these methods were selected the experimental implementation of the methods of Power and Stationary Wave and described the routines that will be used on the test bench of the LABCABOS/UnB